GAZI UNIVERSITY INFORMATION PACKAGE - 2019 ACADEMIC YEAR

COURSE DESCRIPTION

ADVANCED LOGIC CIRCUIT DESIGN/5181329

Course Title:	ADVANCED LOGIC CIRCUIT DESIGN
Credits	3	ECTS	7.5
Semester	1	Compulsory/Elective	Elective

COURSE INFO

-- LANGUAGE OF INSTRUCTION

Turkish

-- NAME OF LECTURER(S)

Prof. Dr. Etem Köklükaya

-- WEB SITE(S) OF LECTURER(S)

-- EMAIL(S) OF LECTURER(S)

-- LEARNING OUTCOMES OF THE COURSE UNIT

Learning of circuit design with programmable logic controllers
Error analysis in logic circuits
Learning of State reduction methods

-- MODE OF DELIVERY

The mode of delivery of this course is Face to face

-- PREREQUISITES AND CO-REQUISITES

There is no prerequisite or co-requisite for this course.

-- RECOMMENDED OPTIONAL PROGRAMME COMPONENTS

There is no recommended optional programme component for this course.

--COURSE CONTENT
1. Week	Equivalence relations
2. Week	Partially ordered sets
3. Week	mesh structures
4. Week	Boolean algebra
5. Week	state reduction in certain cases completely sequential machine
6. Week	state reduction in certain cases completely sequential machine
7. Week	state reduction in certain cases completely sequential machine
8. Week	Circuit design with Field Programmable Gate Arrays
9. Week	Circuit design with Field Programmable Gate Arrays
10. Week	The design of asynchronous sequential circuits
11. Week	Circuit design with programmable logic controllers
12. Week	Circuit design with programmable logic controllers
13. Week	Error analysis in logic circuits
14. Week	Error analysis in logic circuits
15. Week
16. Week

-- RECOMMENDED OR REQUIRED READING

[1] SAZHINA, N. and GRUSHINSKY, N., 1971. Gravity Prospecting. Mir Publishers, Moscow [2] Sayısal Sistem Tasarımı Bülent Sankur, Yorgo istefenapolos [3] Ardışıl Lojik Devreler II Emin Ünalan [4] G. De Micheli, Synhesis and Optimization of Digital Circuits, McGraw-Hill, [5] R. Murgai, R.K. Brayton and Sangiovanni-Vincentelli, Logic Synthesis for Field Programmable Gate Arrays, Kluwer Academic Publishers, 1995. [6] S. Brown, Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 2000.

-- PLANNED LEARNING ACTIVITIES AND TEACHING METHODS

Lecture, Question & Answer, Demonstration, Drill - Practise

-- WORK PLACEMENT(S)

Not Applicable

-- ASSESSMENT METHODS AND CRITERIA

	Quantity	Percentage
Mid-terms	1	30
Assignment	1	10
Exercises	0	0
Projects	0	0
Practice	0	0
Quiz	0	0
Contribution of In-term Studies to Overall Grade		40
Contribution of Final Examination to Overall Grade		60

-- WORKLOAD

Efficiency	Total Week Count	Weekly Duration (in hour)	Total Workload in Semester
Theoretical Study Hours of Course Per Week	14	3	42
Practising Hours of Course Per Week			0
Reading	10	3	30
Searching in Internet and Library	10	3	30
Designing and Applying Materials	10	3	30
Preparing Reports			0
Preparing Presentation			0
Presentation			0
Mid-Term and Studying for Mid-Term	5	3	15
Final and Studying for Final	5	3	15
Other	10	3	30
TOTAL WORKLOAD:			192
TOTAL WORKLOAD / 25:			7.68
ECTS:			7.5

-- COURSE'S CONTRIBUTION TO PROGRAM

NO	PROGRAM LEARNING OUTCOMES	1	2	3	4	5
1						X
2					X
3					X
4					X
5					X
6					X
7					X
8					X
9					X
10					X
11						X
12					X

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GAZI UNIVERSITY INFORMATION PACKAGE - 2019 ACADEMIC YEAR